H8S56 Datasheet, PDF (406/980 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 11 8-Bit Timers (TMR)
Initial
Bit Bit Name Value R/W Description
4 CCLR1 0
R/W Counter Clear 1 and 0
3 CCLR0 0
R/W These bits select the method by which TCNT is cleared
00: Clearing is disabled
01: Cleared on compare-match A
10: Cleared on compare-match B
11: Cleared on rising edge of external reset input
2 CKS2
0
R/W Clock Select 2 to 0
1 CKS1
0
0 CKS0
0
R/W The input clock can be selected from three clocks divided
R/W ^{from the system clock (φ). When use of an external clock is}
selected, three types of count can be selected: at the rising
edge, the falling edge, and both rising and falling edges.
000: Clock input disabled
001: φ/8 internal clock source, counted on the falling edge
010: φ/64 internal clock source, counted on the falling edge
011: φ/8192 internal clock source, counted on the falling
edge
100: For channel 0: Counted on TCNT1 overflow signal*
For channel 1: Counted on TCNT0 compare-match A
signal*
For channel 2: Counted on TCNT3 overflow signal*
For channel 3: Counted on TCNT2 compare-match A
signal*
101: External clock source, counted at rising edge
110: External clock source, counted at falling edge
111: External clock source, counted at both rising and
falling edges
Note: * If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and
that of channel 1 (channel 3) is the TCNT0 (TCNT2) compare-match signal, no
incrementing clock will be generated. Do not use this setting.
Rev. 6.00 Sep. 24, 2009 Page 358 of 928
REJ09B0099-0600