H8S56 Datasheet, PDF (395/980 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.9.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation will be that in the buffer prior to the write.
Figure 10.48 shows the timing in this case.
TGR write cycle
T1
T2
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
Buffer register
address
Buffer register write data
N
M
N
Figure 10.48 Contention between Buffer Register Write and Compare Match
Rev. 6.00 Sep. 24, 2009 Page 347 of 928
REJ09B0099-0600