H8S56 Datasheet, PDF (373/980 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2500 Series

Section 10 16-Bit Timer Pulse Unit (TPU)
10.4.6 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of the TPSC0 to TPSC2 bits and
CKEG0 and CKEG1 bits in TCR. However, the functions of the CCLR0 and CCLR1 bits in TCR,
and of TIOR, TIER, and TGR, are valid, and input capture/compare match and interrupt functions
can be used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in TSR is set; if underflow occurs
when TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 10.31 shows the correspondence between external clock pins and channels.
Table 10.31 Phase Counting Mode Clock Input Pins
Channels
When channel 1 or 5 is set to phase counting mode
When channel 2 or 4 is set to phase counting mode
External Clock Pins
A-Phase
B-Phase
TCLKA
TCLKB
TCLKC
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 10.24 shows an example of the
phase counting mode setting procedure.
Rev. 6.00 Sep. 24, 2009 Page 325 of 928
REJ09B0099-0600