NP90N04PUF_15 Datasheet, PDF (4/9 Pages) Renesas Technology Corp – SWITCHING N-CHANNEL POWER MOS FET

NP90N04PUF
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate to Source Threshold Voltage
Forward Transfer Admittance ^Note
Drain to Source On-state Resistance ^Note
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Turn-off Delay Time
Fall Time
Total Gate Charge
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage ^Note
Reverse Recovery Time
Reverse Recovery Charge
IDSS
IGSS
VGS(th)
| yfs |
RDS(on)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QG
QGS
QGD
VF(S-D)
trr
Qrr
VDS = 40 V, VGS = 0 V
VGS = ±20 V, VDS = 0 V
VDS = VGS, ID = 250 µA
VDS = 10 V, ID = 45 A
VGS = 10 V, ID = 45 A
VDS = 25 V
VGS = 0 V
f = 1 MHz
VDD = 20 V, ID = 45 A
VGS = 10 V
RG = 0 Ω
VDD = 32 V
VGS = 10 V
ID = 90 A
IF = 90 A, VGS = 0 V
IF = 90 A, VGS = 0 V
di/dt = 100 A/µs
Note Pulsed
MIN. TYP. MAX. UNIT
1
µA
±100 nA
2.0 2.8 4.0 V
31 62
S
2.5 3.0 mΩ
6500 9750 pF
1000 1500 pF
330 595 pF
37 81 ns
14 35 ns
75 150 ns
12 30 ns
110 165 nC
26
nC
30
nC
0.9 1.5 V
54
ns
85
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
BVDSS
IAS
ID
VDD
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
RG
PG.
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1%
RL
VDD
VGS
VGS
Wave Form
10%
0
VDS
90%
VDS
VDS
0
Wave Form
td(on)
VGS
90%
90%
10% 10%
tr td(off) tf
ton
toff
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
2
Data Sheet D16717EJ1V0DS