H8S2110B Datasheet, PDF (372/559 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer Renesas H8S Family/H8S/2100 Series

Section 13 I²C Bus Interface (IIC)
If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC
counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter
value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.21.)
ASD
SCL
A
Transmit/receive data
A
Transmit/receive
data
SCL =
9 1 2 3 4 5 6 7 8 _{‘L’ confirm} 9 1 2 3
BC2–BC0
0
IRIC
(operation
example)
7 6 5 4 3 21
IRIC flag clear available
0
7
IRIC clear
65
When BC2-0 ≥ 2
IRIC clear
IRIC flag clear available
IRIC flag clear unavailable
Figure 13.32 IRIC Flag Clear Timing on WAIT Operation
11. Note on IRIC flag clear when the wait function is used
If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be
inserted by driving the SCL pin low is used when the wait function is used in I²C bust interface
master mode, the IRIC flag should be cleared after determining that the SCL is low, as
described below.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
Secures a high period
SCL
VIH
SCL = low detected
SDA
IRIC
[1] SCL = low determination
[2] IRIC clear
Figure 13.33 IRIC Flag Clearing Timing When WAIT = 1
Rev. 2.00 Mar 21, 2006 page 334 of 518
REJ09B0299-0200