PD780701Y_15 Datasheet, PDF (37/66 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD780701Y, 780702Y
The IEBus is broadly configured from the following 6 blocks.
• CPU interface
• Interrupt control
• Internal registers
• Bit processing
• Field processing
• IEBus interface
<CPU interface>
This is a control block whose purpose is to interface between the CPU (78K/0) and the IEBus main unit.
<Interrupt control>
This is a control block whose purpose is to pass on interrupt request signals from the IEBus main unit to the CPU.
<Internal registers>
This block sets the control registers that control the IEBus and the data of each field.
<Bit processing>
This block performs the bit timing generation and resolution, and is mainly configured from bit sequence ROM, an
8-bit preset timer, and a determiner.
<Field processing>
This block generates each field in the communication frame, and is mainly configured from field sequence ROM, a
4-bit down counter, and a determiner.
<IEBus interface>
This is the external driver/receiver interface block, and is mainly configured from a noise filter, a shift register, a
contention detector, a parity detector, a parity generation circuit, and an ACK/NACK generation circuit.
Preliminary Product Information U13920EJ1V0PM00
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