PD780701Y_15 Datasheet, PDF (34/66 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCONTROLLER

µPD780701Y, 780702Y
Figure 4-16. DCAN Controller Block Diagram (µPD780701Y only)
Memory
access
CPU
Cycle steal
DMA control
SFR access
High-speed
RAM
Interface
management
(including
global register)
Timer
Time signal
DCAN interface
Arbitration
Memory
access engine
DCAN
protocol
Receive message
Receive message
Receive message
Receive
message
Buffer RAM
for DCAN
Transmit buffer
Transmit
buffer
External bus
transceiver
CANL
CANH
The DCAN interface section processes all protocol operations by means of the DCAN protocol section hardware.
The memory access engine either fetches the DCAN protocol data transmitted from a specific RAM area and
transfers it to the DCAN protocol section, or compares and sorts the fetched data and then stores it in a predefined
RAM area.
The DCAN allows direct interfacing between the DCAN and the accessible CPU area, as well as between the CPU
and that area without any effect on the CPU. The DCAN section operates with the external bus transceiver that
converts transmit data line and receive data line to the electrical characteristics of DCAN bus.
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Preliminary Product Information U13920EJ1V0PM00