R8C25 Datasheet, PDF (360/525 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/24 Group, R8C/25 Group
16. Clock Synchronous Serial Interface
Slave Address Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
SAR
Bit Symbol
FS
Address
00BDh
Bit Name
Format select bit
SVA0
SVA1
SVA2
SVA3
SVA4
SVA5
SVA6
Slave address 6 to 0
After Reset
00h
Function
RW
0 : I²C bus format
1 : Clock synchronous serial format
RW
Set an address dif f erent f rom that of the other
RW
slave devices w hich are connected to the I²C
RW
bus. When the 7 high-order bits of the first frame _RW
transmitted after the starting condition match bits _RW
SVA0 to SVA6 in slave mode of the I²C bus
RW
format, the MCU operates as a slave device.
RW
RW
IIC bus Transmit Data Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
ICDRT
00BEh
FFh
Function
RW
Store transmit data
When it is detected that the ICDRS register is empty, the stored transmit data item is
transferred to the ICDRS register and data transmission starts.
When the next transmit data item is w ritten to the ICDRT register during transmission of the
RW
data in the ICDRS register, continuous transmit is enabled. When the MLS bit in the ICMR
register is set to 1 (data transferred LSB-first) and after the data is w ritten to the ICDRT
register, the MSB-LSB inverted data is read.
Figure 16.29 Registers SAR and ICDRT
Rev.3.00 Feb 29, 2008 Page 343 of 485
REJ09B0244-0300