R8C25 Datasheet, PDF (248/525 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Control Register 0⁽³⁾
b7 b6 b5 b4 b3 b2 b1 b0
001
Symbol
Address
After Reset
TRDCR0
0140h
00h
Bit Symbol
Bit Name
Function
RW
Count source select bits
b2 b1b0
TCK0
0 0 0 : f1
RW
0 0 1 : f2
0 1 0 : f4
TCK1
0 1 1 : f8
RW
1 0 0 : f32
1 0 1 : TRDCLK input⁽¹⁾
TCK2
1 1 0 : fOCO40M
1 1 1 : Do not set.
RW
External clock edge select bits^{(2) b4 b3}
CKEG0
0 0 : Count at the rising edge
RW
0 1 : Count at the falling edge
1 0 : Count at both edges
CKEG1
1 1 : Do not set.
RW
CCLR0
CCLR1
CCLR2
TRD0 counter clear select bits Set to 001b (TRD0 register cleared at compare RW
match w ith TRDGRA0 register) in reset
RW
synchronous PWM mode.
RW
NOTES:
1. This setting is enabled w hen the STCLK bit in the TRDFCR register is set to 1 (external clock input enabled).
2. Bits CKEG1 to CKEG0 are enabled w hen bits TCK2 to TCK0 are set to 101b (TRDCLK input) and the STCLK bit in the
TRDFCR register is set to 1 (external clock input enabled).
3. The TRDCR1 register is not used in reset synchronous PWM mode.
Figure 14.79 TRDCR0 Register in Reset Synchronous PWM Mode
Rev.3.00 Feb 29, 2008 Page 231 of 485
REJ09B0244-0300