R8C25 Datasheet, PDF (208/525 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/24 Group, R8C/25 Group
14. Timers
Timer RD Status Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
TRDSR0
TRDSR1
0143h
0153h
Bit Symbol
Bit Name
Input capture/compare match
flag A
IMFA
After Reset
11100000b
11000000b
Function
RW
[Source for setting this bit to 0]
Write 0 after read⁽²⁾
[Source for setting this bit to 1]
TRDSR0 register:
fOCO128 signal edge w hen the IOA3 bit in the
TRDIORA0 register is set to 0 (fOCO128 signal)
TRDIOA0 pin input edge w hen the IOA3 bit in the RW
TRDIORA0 register is set to 1 (TRDIOA0 input)⁽³⁾
TRDSR1 register:
Input edge of TRDIOA1 pin⁽³⁾
IMFB
IMFC
IMFD
OVF
UDF
Input capture/compare match [Source for setting this bit to 0]
flag B
Write 0 after read⁽²⁾
[Source for setting this bit to 1]
RW
Input edge of TRDIOBi pin⁽³⁾
Input capture/compare match [Source for setting this bit to 0]
flag C
Write 0 after read⁽²⁾
[Source for setting this bit to 1]
RW
Input edge of TRDIOCi pin⁽⁴⁾
Input capture/compare match [Source for setting this bit to 0]
flag D
Write 0 after read⁽²⁾
[Source for setting this bit to 1]
RW
Input edge of TRDIODi pin⁽⁴⁾
Overflow flag
[Source for setting this bit to 0]
Write 0 after read⁽²⁾
[Source for setting this bit to 1]
RW
When the TRDi register overflow s
Underflow flag⁽¹⁾
This bit is disabled in the input capture function.
RW
—
Nothing is assigned. If necessary, set to 0.
(b7-b6) When read, the content is 1.
—
NOTES:
1. Nothing is assigned to b5 in the TRDSR0 register. When w riting to b5, w rite 0. When reading, the content is 1.
2. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1 even
if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
3. Edge selected by bits IOj1 to IOj0 (j = A or B) in the TRDIORAi register.
4. Edge selected by bits IOk1 to IOk0 (k = C or D) in the TRDIORCi register
Including w hen the BFki bit in the TRDMR register is set to 1 (TRDGRki is used as the buffer register).
Figure 14.40 Registers TRDSR0 to TRDSR1 in Input Capture Function
Rev.3.00 Feb 29, 2008 Page 191 of 485
REJ09B0244-0300