E1 Datasheet, PDF (34/50 Pages) Renesas Technology Corp – E1/E20 Emulator

E1/E20 Emulator
Designing the User System
2.5.10. About the FINEC and MD/FINED Pins
For the RX63x Group, FINE interface only supports a 2-wire system using FINEC and MD/FINED pins.
In FINE Interface Connection, the emulator uses the FINEC and MD/FINED pins. Any functions that are
multiplexed on the FINEC pin are not available.
For the RX200 Series and RX100 Series, FINE interface supports a 1-wire system using the MD/FINED pin.
Only the MD/FINED pin is exclusively used by the E1 or E20 emulator. It is not necessary to connect the FINEC
pin since this pin is not used. The FINEC pin can be used as a port.
Pull up the MD/FINED signal at 4.7 kΩ. Pull up the FINEC signal at 4.7 kΩ to 10 kΩ. Do not arrange these signal
lines in parallel with or across other high-speed signal lines.
Connector
FINEC
VCC
4.7kΩ
to 10 kΩ
VCC
4.7kΩ
FINEC
MCU
MD/FINED
MD/FINED
Figure 2.24 Connection of the FINEC and MD/FINED Pins to the E1 or E20
Do not use adjacent resistors for pull-up of the TCK pin because they may affect or may be affected from other
pins.
For the FINEC pin, add a grounded guard ring to the pattern between the emulator connector and the MCU.
Do not install capacitors, series resistors, or filters on signal lines; if attempted, correct communication may not
be established.
2.5.11. About the TRCLK, TRSYNC, and TRDATA0 to TRDATA3 Pins
The TRCLK, TRSYNC, and TRDATA0 to TRDATA3 pins are intended for the acquisition of large amounts of
trace data when the E20 is in use with a 38-pin connector. The trace signals (TRCLK, TRSYNC, and TRDATA0 to
TRDATA3) operate at high speed. Make the lengths of these signal lines as uniform as is possible (keeping the
variation within 10 mm is recommended). Do not split the signal lines or wire any other signal line close to these
lines and make the lines as short as possible. Pull up the TRCLK, TRSYNC, and TRDATA0 to TRDATA3 signal at
4.7 kΩ to 10 kΩ. Do not arrange these signal lines in parallel with or across other high-speed signal lines.
Connector
TRCLK,
TRSYNC,
TRDATA0,
TRDATA1,
TRDATA2,
TRDATA3
VCC
4.7kΩ to 10 kΩ
Figure 2.25 Connection of the Trace Pins to the E20
MCU
Trace signals (TRCLK, TRSYNC, and TRDATA0 to TRDATA3) operate at high speed. Do not place any devices
that will produce noise over these lines.
For the TRCLK pin, add a grounded guard ring to the pattern between the connector and the MCU.
Do not install capacitors, series resistors, or filters on signal lines; if attempted, correct communication may not
be established.
R20UT0399EJ0700 Rev.7.00
Feb 01, 2014
Page 34 of 50