M32C88 Datasheet, PDF (319/461 Pages) Renesas Technology Corp – RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/88 Group (M32C/88T)
22. CAN Module
22.1 CAN-Associated Registers
Figures 22.3 to 22.18, and Figures 22.20 to 22.33 show registers associated with CAN. To access the
CAN-associated registers, set the CM21 bit in the CM2 register to "0" (main clock or PLL clock as CPU
clock) and the MCD4 to MCD0 bits in the MCD register to "100102" (no division mode). Or, set the PM24 bit
in the PM2 register to "1" (main clock direct mode) and the PM25 bit in the PM2 regiseter to "1" (CAN clock).
Two wait states are added into the bus cycle.
Refer to 7. Processor Mode and 8. Clock Generation Circuit.
22.1.1 CANi Control Register 0 (CiCTLR0 Register) (i=0 to 2)
CANi Control Register 0 (i=0 to 2)
Symbol
Address
b15
b8 b7
b0
C0CTLR0
020116 - 020016
0
C1CTLR0
028116 - 028016
C2CTLR0
01A116 - 01A016
After Reset⁽¹⁾
XXXX 0000 XX01 0X012
XXXX 0000 XX01 0X012
XXXX 0000 XX01 0X012
Bit
Symbol
Bit Name
Function
RW
RESET0 CAN Reset Bit 0
0: CAN module reset exited
1: CAN module is reset⁽²⁾
RW
Loop Back Mode 0: Disables loop back function
LOOPBACK _{Select Bit}
1: Enables loop back function
RW
Nothing is assigned. When write, set to "0".
(b2) ^{When read, its content is indeterminate.}
BasicCAN Mode 0 : Disables BasicCAN mode function
BASICCAN _{Select Bit}
1 : Enables BasicCAN mode function
RW
0: CAN module reset exited
RESET1 CAN Reset Bit 1
1: CAN module is reset⁽²⁾
RW
Reserved Bit
Set to "0".
RW
(b5)
Nothing is assigned. When write, set to "0".
(b7 - b6) When read, its content is indeterminate.
TSPRE0
TSPRE1
Time Stamp
Prescaler Select Bit
b9 b8
0 0: Selects the CAN bus bit clock
RW
0 1: Selects the CAN bus bit clock divided by 2
1 0: Selects the CAN bus bit clock divided by 3 _RW
1 1: Selects the CAN bus bit clock divided by 4
Time Stamp
TSRESET
Counter Reset Bit
ECRESET ^{Error Counter}
Reset Bit
0: Nothing is occurred
1: This bit is automatically set to "0" after _RW
the CiTSR register is set to "000016"⁽³⁾
0: Nothing is occurred
1: This bit is automatically set to "0" after
the CiTEC and CiREC registers are
RW
set to "0016"⁽³⁾
Nothing is assigned. When write, set to "0".
(b15 - b12) When read, its content is indeterminate.
NOTES:
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after reset
and supplying a clock to the CAN module.
2. Set the RESET1 and RESET0 bits to the same value simultaneously.
3. These bits can only be set to "1", not "0", by program.
Figure 22.3 C0CTLR0, C1CTLR0 and C2CTLR0 Registers
Rev. 1.10 Oct. 18, 2005 ^{Page 296} of 435
REJ09B0162-0110