M32C88 Datasheet, PDF (291/461 Pages) Renesas Technology Corp – RENESAS 16/32-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M32C/80 SERIES

M32C/88 Group (M32C/88T)
21. Intelligent I/O
(1) Free-Running Operation
(The RST2 and RST1 bits in the G1BCR1 register are set to "002")
FFFF16
Base Timer
m
000016
"H"
OUTC1j pin⁽¹⁾
"L"
"H"
OUTC1j pin⁽²⁾
"L"
PO1jR bit in the ^"1"
IIOiIR register
"0 "
65536
fBT1
Inverse
Inverse
Write "0" by program
if setting to "0"
65536
fBT1
Inverse
65536 x 2
fBT1
Inverse
i=0 to 4, 8 to 10; j=0 to 7
m: Setting value of the G1POj register, 000016 to FFFF16
NOTES:
1. Waveform output when the INV bit in the G1POCRj register is set to "0" (not inversed)
and the IVL bit in the G1POCRj register is set to "0" ("L" output as default value).
2. Waveform output when the INV bit is set to "0" (not inversed) and the IVL bit is set to "1"
("H" output as default value).
The above applies under the following condition:
• The RST2 and RST1 bits in the G1BCR1 register are set to "002" (no base timer reset)
and the UD1 and UD0 bits in the G1BCR1 register to "002" (counter increment mode).
(2) The Base Timer is Reset when the Base Timer Matches the G1PO0 Register
(The RST1 bit is set to "1" and the RST2 bit is set to "0")
n+2
Base Timer
m
000016
m
fBT1
OUTC1j pin
"H"
"L"
n+2
fBT1
Inverse
n+2
fBT1
Inverse
Inverse
PO1jR bit in the "1"
IIOiIR register
"0"
Write "0" by
program if
setting to "0"
2(n+2)
fBT1
i=0 to 4, 8 to 10; j=1 to 7
m: Setting value of the G1POj register, 000016 to FFFF16
n: Setting value of the G1PO0 register, 000116 to FFFD16
The above applies under the following conditions:
• The IVL bit in the G1POCRj register is set to "0" ("L" output as default value) and
the INV bit is set to "0" (not inversed).
• The UD1 and UD0 bits are set to "002" (counter increment mode).
• m<n+2
Figure 21.17 Phase-delayed Waveform Output Mode
Rev. 1.10 Oct. 18, 2005 ^{Page 268} of 435
REJ09B0162-0110