H83024 Datasheet, PDF (303/841 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 8 16-Bit Timer
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal. The value
before the counter is cleared is transferred to the general register. See figure 8.43.
φ
Input capture signal
Counter clear signal
16TCNT input clock
16TCNT
N
H'0000
GR
N
Figure 8.43 Contention between Counter Clearing by Input Capture and Counter
Increment
Rev. 2.00 Sep 20, 2005 page 265 of 800
REJ09B0260-0200