H83024 Datasheet, PDF (186/841 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Series

Section 6 Bus Controller
CPU cycles
External bus released CPU cycles
T0
T1
T2
φ
Address bus
Data bus
AS
Address
High-impedance
High-impedance
High-impedance
RD
HWR, LWR
BREQ
High
High-impedance
High-impedance
BACK
Minimum 3 cycles
(1)
(2)
(3)
(4)
(5)
(6)
Figure 6.20 Example of External Bus Master Operation
When making a transition to software standby mode, if there is contention with a bus request from
an external bus master, the BACK and strobe states may be indefinite when the transition is made.
When using software standby mode, clear the BRLE bit to 0 in BRCR before executing the
SLEEP instruction.
Rev. 2.00 Sep 20, 2005 page 148 of 800
REJ09B0260-0200