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M16C5M Datasheet, PDF (29/159 Pages) Renesas Technology Corp – RENESAS MCU
M16C/5M Group, M16C/57 Group
2. Central Processing Unit (CPU)
2.8.7 Interrupt Enable Flag (I Flag)
The I flag enables maskable interrupts.
Maskable interrupts are disabled when the I flag is 0, and enabled when it is 1. The I flag becomes 0
when an interrupt request is accepted.
2.8.8 Stack Pointer Select Flag (U Flag)
ISP is selected when the U flag is 0. USP is selected when the U flag is 1.
The U flag becomes 0 when a hardware interrupt request is accepted, or the INT instruction of software
interrupt number 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from 0 to 7.
If a requested interrupt has higher priority than IPL, the interrupt request is enabled.
2.8.10 Reserved Areas
Only set these bits to 0. The read value is undefined.
REJ03B0267-0101 Rev.1.01
Jul 23, 2010
Page 29 of 156