H83297 Datasheet, PDF (28/393 Pages) Renesas Technology Corp – Single-Chip Microcomputer

Table 1-3 Pin Functions (cont)
Type
Data bus
Symbol
D₇ to D₀
Bus
control
WAIT
RD
WR
AS
Interrupt NMI
signals
Operating
mode
control
IRQ₀ to
IRQ₂
MD₁,
MD₀
Pin No.
DC-64S
DP-64S FP-64A TFP-80C I/O Name and function
64 to 57 56 to 49 65 to 61, I/O Data bus: 8-Bit bidirectional data bus.
69 to 67
8
64
80
I Wait: Requests the CPU to insert wait
states into the bus cycle when an
external address is accessed.
4
60
75
O Read: Goes Low to indicate that the
CPU is reading an external address.
5
61
77
O Write: Goes Low to indicate that the
CPU is writing to an external address.
6
62
78
O Address strobe: Goes Low to
indicate that there is a valid address
on the address bus.
13
5
5
I Nonmaskable interrupt: Highest-
priority interrupt request. The NMIEG
bit in the system control register
(SYSCR) determines whether the
interrupt is recognized at the rising or
falling edge of the NMI input.
1 to 3 57 to 59 71, 72, 74 I Interrupt request 0 to 2: Maskable
interrupt request pins.
19,
11,
14,
20
12
16
I Mode: Input pins for setting the MCU
operating mode according to the table
below.
MD₁ MD₀ Mode Description
0 1 Mode 1 Expanded mode
with on-chip ROM
disabled
1 0 Mode 2 Expanded mode
with on-chip ROM
enabled
1 1 Mode 3 Single-chip mode
13