H83297 Datasheet, PDF (169/393 Pages) Renesas Technology Corp – Single-Chip Microcomputer

(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T₃ state of a write cycle to the lower byte of the free-running counter, the write takes
priority and FRC is not incremented.
Figure 8-17 shows this type of contention.
Write cycle:
CPU write to lower byte of FRC
T₁
T₂
T₃
ø
Internal address bus
FRC address
Internal write signal
FRC clock pulse
FRC
N
M
Write data
Figure 8-17 FRC Write-Increment Contention
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