H83297 Datasheet, PDF (215/393 Pages) Renesas Technology Corp – Single-Chip Microcomputer

Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER
0
1
Description
To clear ORER, the CPU must read ORER after it has been set to 1,
then write a 0 in this bit.
This bit is set to 1 if reception of the next character ends while
the receive data register is still full (RDRF = 1).
(Initial value)
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4
FER
0
1
Description
To clear FER, the CPU must read FER after it has been set to 1,
then write a 0 in this bit.
This bit is set to 1 if a framing error occurs (stop bit = 0).
(Initial value)
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without parity
bits is used.
Bit 3
PER
0
1
Description
To clear PER, the CPU must read PER after it has been set to 1,
then write a 0 in this bit.
(Initial value)
This bit is set to 1 when a parity error occurs (the parity of the received data does not
match the parity selected by the O/E bit in SMR).
200