HD64F2134ATF20 Datasheet, PDF (27/39 Pages) Renesas Technology Corp – E6000 Emulator HS2148EPI61H Supplementary Information

Section 3 Notes on Use
3.1 I/O Register Differences between Actual MCU and E6000
In the E6000, one evaluation chip emulates several types of MCU. Therefore, there are some
differences in I/O registers between an actual MCU and the E6000. Note these differences when
accessing the I/O registers.
I/O port is in the input state at default. The I/O register contents indicate the emulator port status.
When the user system interface cable is not connected, the read value is 1 due to pull-up resistors.
In the E6000, accesses to the following registers for controlling the flash memory in the H8S/2148,
H8S/2138, H8S/2128 series, H8S/2149, H8S/2169 are invalid.
· Flash memory control register 1 (FLMCR1: FF80)
· Flash memory control register 2 (FLMCR2: FF81)
· Erase block register 1 (EBR1: FF82)
· Erase block register 2 (EBR2: FF83)
· Serial timer control register (STCR: H'FFC3)
(Accesses to the FLSHE bit are invalid)
3.2 Access to the Reserved Area and Internal RAM
When accessing the reserved area and internal RAM, note the following:
1. Part of the reserved area (specified in each MCU’s memory map) can be used as an external
address area when the RAME bit of the SYSCR is cleared to 0. Target (user memory) or
Emulator (optional memory) can be specified for this area with the Configuration settings.
2. If the reserved area other than that described in item 1 above is used, the operation in the actual
MCU cannot be guaranteed. If the user program extends to the reserved area during
debugging, select the MCU having the largest ROM capacity (for example, debug the
H8S/2144 program in the H8S/2148 mode).
3. Internal RAM (specified in each MCU’s memory map) can be used as an external address area
when the RAME bit of the SYSCR is cleared to 0. Target (user memory) can be specified for
this area with the Configuration settings.