HD49335NP Datasheet, PDF (27/30 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49335NP/HNP
Example of Recommended External Circuit
• Slave mode
Pin 57(Test1 = Low)
3.0V
47µ
47/6 ⁺ 0.1
47µ
to CCD
Pin 57
Mode
Specification
Low Slave mode CLK, HD, VD input from SSG.
Hi Master mode HD, VD output
∗ Pin 56 = Low: TESTIN mode. Please do not use.
Reset(Normally Hi)
0.1
to V.Baff
to CCD
33k
0.1
0.1
0.1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
XV3
VD_in
33 XV4
34 CH1
35 CH2
36 CH3
37 CH4
38 XSUB
39 SUB_SW/ADCK_in
40 SUB_PD
41 STROB/Vgate
42 DV_SS3
43 AV_SS
44 ADC_in
45 BIAS
46 VRB
47 VRT
48 VRM
HD49335
HD_in 16
CLK_in 15
DV_SS3 14
DV_DD2 13
D9 12
D8 11
D7 10
D6 9
D5 8
D4 7
D3 6
D2 5
D1 4
D0 3
DV_SS1,2 2
ID 1
from
Pulse generator
to
Camera
signal
processor
ID pulse
AV_DD
SCK
47µ
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
∗ 61pin = Low: Pin 41 is STROB output
+
0.1
47/6
1µ 1µ
Pin 39 is SUB_SW output
0.1
47/6 ^{61pin = Hi: Pin 41 is Vgate output}
Pin 39 is Hiz
CCD signal input ^1000p
100p
Serial data input
• Master mode
Pin 57(Test1 = Hi)
3.0V
47µ
47/6 ⁺ 0.1
47µ
to CCD
Reset(Normally Hi)
0.1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
XV3
VD_in
to V.Baff
to CCD
33k
0.1
0.1
0.1
33 XV4
34 CH1
35 CH2
36 CH3
37 CH4
38 XSUB
39 SUB_SW/ADCK_in
40 SUB_PD
41 STROB/Vgate
42 DV_SS3
43 AV_SS
44 ADC_in
45 BIAS
46 VRB
47 VRT
48 VRM
HD49335
HD_in 16
CLK_in 15
DV_SS3 14
DV_DD2 13
D9 12
D8 11
D7 10
D6 9
D5 8
D4 7
D3 6
D2 5
D1 4
D0 3
DV_SS1,2 2
ID 1
AV_DD
SCK
47µ
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
+
0.1
47/6
1µ 1µ
0.1
1000p
CCD signal input
100p
Serial data input
to
Camera
signal
processor
from
Pulse generator
to
Camera
signal
processor
ID pulse
∗ 61pin = Low: Pin 41 is STROB output
Pin 39 is SUB_SW output
47/6 ^{61pin = Hi: Pin 41 is Vgate output}
Pin 39 is Hiz
Unit: R: Ω
C: F
Rev.1.0, Feb.12.2004, page 27 of 29