HD49335NP Datasheet, PDF (17/30 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49335NP/HNP
Serial Interface Specifications
Timing Specifications
t_INT1
Latches SDATA
CS
at SCK rising edge
f_SCK
Data is determined
at CS rising edge
t_INT2
SCK
t_su
SDATA
t_ho
D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
STD2(Upper data)
STD1(Lower data)
address(address)
Item
fSCK
tINT1,2
tsu
tho
Min
—
50 ns
50 ns
50 ns
Figure 8 Serial Interface Timing Specifications
Max
5 MHz
—
—
—
Notes: 1. 3 byte continuous communications.
2. Input SCK with 24 clock when CS is Low.
3. It becomes invalid when data communications are stopped on the way.
4. Data becomes a default with hardware reset.
5. Input more than double frequency of SCK to the CLK_in when transfer
the serial data.
The Kind of Data
Data address has 256 type. H’00 to H’FF
H’00
:
:
H’EF
Data at timing generator part
H’F0
:
:
H’FF
Data at CDS part
Address map of each data referred to other sheet.
Details of timing generator refer to the timing chart on the other sheet together with this specification.
This specification only explains about the data of CDS part.
Rev.1.0, Feb.12.2004, page 17 of 29