HD49335NP Datasheet, PDF (21/30 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49335NP/HNP
Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in
parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss
quantization) occurs to the image.
Differential code and gray code are recommended for this countermeasure.
Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital
output bit can be reduced and easily to reduce the ripple using this function.
This function is especially effective for longer the settings of sensor more than clk = 30 kHz, and ADC output.
Figure 11 indicates the timing specifications.
10 ^{Differential SW(D9)}
ADC
2clk_DL
Standard data
control signal
(D12,D11,D10)
+
−
Carry bit
round
Standard
data
selector
Gray SW(D8)
Gray→Binary
conversion
Figure 10 Differential Code, Gray Code Circuit
10-bit
output
ADCLK
(In case of select the positive edge of ADCLK with D12)
OBP
(In case of select the positive polar)
(Beginning edge of OBP and standard edge of ADCLK should be exept ±5 ns)
Digital output
1 2 3 4 5 6 7 8 9 10 11
Differential data
Standard
data
Differential data
Figure 11 Differential Code Timing Specifications
To use differential code, complex circuit is necessary at DSP side.
From ADC
Standard data
control signal
Gray →
Binary
Carry bit
round
Standard
data
selector
2clk_DL
D11
D11
D10
D10
D9
D9
D0
D0
(1) Differential coded
(2) Gray → Binary conversion
Figure 12 Complex Circuit Example
Address
STD1[7:0] (L)
1 1 1 1 0 1 0 1 D7 D6 D5 D4 D3 D2 D1 D0
STD2[15:8] (H)
D12 D11 D10 D9 D8
P_RG P_ADCLK P_SP2 P_SP1
DLL
current
DLL
steps
Address
11111000
STD1[7:0] (L)
STD2[15:8] (H)
D6 D5 D4
D2 D1 D0 D15 D14 D13 D12
D10 D9 D8
P_SP2
P_SP1 2,3 divided P_RG
select
P_ADCLK
Rev.1.0, Feb.12.2004, page 21 of 29