HD49335NP Datasheet, PDF (15/30 Pages) Renesas Technology Corp – CDS/PGA & 10-bit A/D TG Converter

HD49335NP/HNP
Electrical Characteristics (cont.)
(Unless othewide specified, Ta = 25°C, AV_DD = 3.0 V, DV_DD = 3.0 V, and R_BIAS = 33 kΩ)
• Items for CDSIN Input Mode
Item
Symbol Min
Typ
Max
Unit Test Conditions
Remarks
Consumption current (1)
IDD1
—
84
96.6
mA fCLK = 36 MHz
CDSIN mode
LoPwr = low
Consumption current (2)
IDD2
—
58
66.7
mA fCLK = 20 MHz
CDSIN mode
LoPwr = high
CCD offset tolerance range
Timing specifications (1)
Timing specifications (2)
Timing specifications (3)
Timing specifications (4)
Timing specifications (5)
VCCD
tCDS1
tCDS2
tCDS3
tCDS4
tCDS5
(–100)
—
Typ × 0.8
—
Typ × 0.8
Typ × 0.85
—
(1.5)
1/4fCLK
(1.5)
1/4fCLK
1/2fCLK
(100)
mV
—
ns
Typ × 1.2 ns
—
ns
Typ × 1.2 ns
Typ × 1.15 ns
Refer to table 8
Timing specifications (6)
tCDS6
1
Timing specifications (7)
tCDS7
—
Timing specifications (8)
tCDS8
—
Timing specifications (9)
tCHLD9
—
Timing specifications (10) tCOD10
—
5
9
1/2fCLK
—
1/2fCLK
—
(7)
—
(16)
—
ns
ns
ns
ns
CL = 10 pF
ns
CL = 10 pF
Timing specifications (11) tCDS11
—
(1/4fCLK)
—
ns
Timing specifications (12) tCDS12
—
(1/fCLK)
—
ns
Timing specifications (13) tCDS13
—
(1/2fCLK)
—
ns
Clamp level
CLP(00) —
(14)
—
LSB
CLP(09) —
(32)
—
LSB
CLP(31) —
(76)
—
LSB
PGA gain at CDS input
AGC(0)
–4.4
–2.4
–0.4
dB
*1
AGC(63) 4.1
6.1
8.1
dB
AGC(127) 12.5
14.5
16.5
dB
AGC(191) 21.0
23.0
25.0
dB
AGC(255) 29.4
31.4
33.4
dB
DLL operation frequency DLL_2
11
—
25
MHz
*2
DLL_3
7
—
11
MHz
*3
DLL_4
5.5
—
7
MHz
*4
T/G 3/1divided operation CLK_in3 28.6
—
frequency range
28.6
MHz fCLK = 1/3CLK_in3
H Buffer output voltage
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
RG output voltage
VOH
VOL
2.94
2.97
—
—
22
47
2.89
2.94
—
—
50
112
2.91
2.96
—
—
36
78
2.85
2.93
—
—
60
129
2.69
2.86
—
—
115
262
2.81
2.90
—
—
78
141
V
30 mA Buff, IOH = –5 mA
MV 30 mA Buff, IOL = +5 mA
V
14 mA Buff, IOH = –5 mA
MV 14 mA Buff, IOL = +5 mA
V
10 mA Buff, IOH = –3 mA
MV 10 mA Buff, IOL = +3 mA
V
4 mA Buff, IOH = –2 mA
MV 4 mA Buff, IOL = +2 mA
V
2 mA Buff, IOH = –2 mA
mV 2 mA Buff, IOL = +2 mA
V
IOH = –2 mA
mV IOL = +2 mA
Notes: 1. Define digital output full scall with 1 V input as 0 dB.
2. Number of master steps: 60 steps, DLL current High
3. Number of master steps: 40 steps, DLL current Low
4. Number of master steps: 60 steps, DLL current Low
5. Values within parentheses ( ) are for reference.
Rev.1.0, Feb.12.2004, page 15 of 29