R8C29 Datasheet, PDF (263/471 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/28 Group, R8C/29 Group
15. Serial Interface
• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)
UiBRG output
UiC1 register
1
RE bit
0
RXDi
Start bit
D0
D1
Stop bit
D7
Determined to be “L” _{Receive data taken in}
Transfer clock
Reception triggered when transfer clock
is generated by falling edge of start bit
UiC1 register
1
RI bit
0
SiRIC register
1
IR bit
0
Transferred from UARTi receive
register to UiRB register
Set to 0 when interrupt request is accepted, or set by a program
The above timing diagram applies when the register bits are set as follows:
• PRYE bit in UiMR register = 0 (parity disabled)
• STPS bit in UiMR register = 0 (1 stop bit)
i = 0 or 1
Figure 15.12 Receive Timing Example in UART Mode
Rev.2.10 Sep 26, 2008 Page 246 of 441
REJ09B0279-0210