R8C29 Datasheet, PDF (196/471 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/28 Group, R8C/29 Group
14. Timers
Timer RC Status Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRCSR
0123h
01110000b
Bit Symbol
Bit Name
Function
RW
Input capture / compare match flag [Source for setting this bit to 0]
IMFA _A
Write 0 after read.⁽¹⁾
RW
Input capture / compare match flag ^{[Source for setting this bit to 1]}
IMFB _B
Refer to the table below .
RW
Input capture / compare match flag
IMFC _C
RW
Input capture / compare match flag
IMFD _D
RW
—
Nothing is assigned. If necessary, set to 0.
(b6-b4) When read, the content is 1.
—
OVF
Overflow flag
[Source for setting this bit to 0]
Write 0 after read.⁽¹⁾
[Source for setting this bit to 1]
RW
Refer to the table below .
NOTE:
1. The w riting results are as follow s:
• This bit is set to 0 w hen the read result is 1 and 0 is w ritten to the same bit.
• This bit remains unchanged even if the read result is 0 and 0 is w ritten to the same bit. (This bit remains 1
even if it is set to 1 from 0 after reading, and w riting 0.)
• This bit remains unchanged if 1 is w ritten to it.
Bit Symbol
IMFA
Timer Mode
Input capture Function
Output Compare
PWM Mode
PWM2 Mode
Function
TRCIOA pin input edge⁽¹⁾
When the values of the registers TRC and TRCGRA match.
IMFB
TRCIOB pin input edge⁽¹⁾
When the values of the registers TRC and TRCGRB match.
IMFC
IMFD
OVF
TRCIOC pin input edge⁽¹⁾
When the values of the registers TRC and TRCGRC
match.⁽²⁾
TRCIOD pin input edge⁽¹⁾
When the values of the registers TRC and TRCGRD
match.⁽²⁾
When the TRC register overflow s.
NOTES:
1. Edge selected by bits IOj1 to IOj0 (j = A, B, C, or D).
2. Includes the condition that bits BFC and BFD are set to 1 (buffer registers of registers TRCGRA
and TRCGRB).
Figure 14.30 TRCSR Register
Rev.2.10 Sep 26, 2008 Page 179 of 441
REJ09B0279-0210