R8C29 Datasheet, PDF (123/471 Pages) Renesas Technology Corp – RENESAS 16-BIT SINGLE-CHIP MCU R8C FAMILY / R8C/2x SERIES

R8C/28 Group, R8C/29 Group
12. Interrupts
12.1.5 Interrupts and Interrupt Vectors
There are 4 bytes in each vector. Set the starting address of an interrupt routine in each interrupt vector. When
an interrupt request is acknowledged, the CPU branches to the address set in the corresponding interrupt vector.
Figure 12.2 shows an Interrupt Vector.
MSB
LSB
Vector address (L)
Low address
Mid address
Vector address (H)
0000
0000
High address
0000
Figure 12.2 Interrupt Vector
12.1.5.1 Fixed Vector Tables
The fixed vector tables are allocated addresses 0FFDCh to 0FFFFh.
Table 12.1 lists the Fixed Vector Tables. The vector addresses (H) of fixed vectors are used by the ID code
check function. For details, refer to 19.3 Functions to Prevent Rewriting of Flash Memory.
Table 12.1 Fixed Vector Tables
Interrupt Source
Undefined instruction
Overflow
BRK instruction
Address match
Single step⁽¹⁾
Watchdog timer,
Oscillation stop detection,
Voltage monitor 1⁽²⁾,
Voltage monitor 2
Address break⁽¹⁾
(Reserved)
Reset
Vector Addresses
Address (L) to (H)
Remarks
Reference
0FFDCh to 0FFDFh Interrupt on UND
R8C/Tiny Series Software
instruction
Manual
0FFE0h to 0FFE3h Interrupt on INTO
instruction
0FFE4h to 0FFE7h If the content of address
0FFE7h is FFh,
program execution
starts from the address
shown by the vector in
the relocatable vector
table.
0FFE8h to 0FFEBh
12.4 Address Match
Interrupt
0FFECh to 0FFEFh
0FFF0h to 0FFF3h
13. Watchdog Timer
10. Clock Generation Circuit
6. Voltage Detection Circuit
0FFF4h to 0FFF7h
0FFF8h to 0FFFBh
0FFFCh to 0FFFFh
5. Resets
NOTES:
1. Do not use these interrupts. They are for use by development tools only.
2. For N, D version only.
Rev.2.10 Sep 26, 2008 Page 106 of 441
REJ09B0279-0210