R8C20 Datasheet, PDF (256/501 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/2x SERIES

R8C/20 Group, R8C/21 Group
14. Timers
Timer RD Mode Register
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRDMR
0138h
00001110b
Bit Symbol
Bit Name
Function
RW
Timer RD synchronous bit
This bit is disabled in PWM3 mode.
SYNC
RW
—
Nothing is assigned. If necessary, set to 0.
(b3 - b1) When read, the content is 1.
—
BFC0
TRDGRC0 register function
selection bit
0 : General register
1 : Buffer register of TRDGRA0 register
RW
TRDGRD0 register function
BFD0 _{selection bit}
0 : General register
1 : Buffer register of TRDGRB0 register
RW
BFC1
TRDGRC1 register function
selection bit
0 : General register
1 : Buffer register of TRDGRA1 register
RW
BFD1
TRDGRD1 register function
selection bit
0 : General register
1 : Buffer register of TRDGRB1 register
RW
Timer RD Function Control Register
b7 b6 b5 b4 b3 b2 b1 b0
00
00
Symbol
TRDFCR
Bit Symbol
CMD0
Address
013Ah
Bit Name
Combination mode selection bit⁽¹⁾
After Reset
10000000b
Function
RW
Set to 00b (timer mode, PWM mode, or
PWM3 mode) in PWM3 mode.
RW
CMD1
RW
Normal-phase output level selection bit This bit is disabled in PWM3 mode.
OLS0 ^{(enabled in reset synchronous PWM}
RW
mode or complementary PWM mode)
Counter-phase output level selection bit This bit is disabled in PWM3 mode.
OLS1 ^{(enabled in reset synchronous PWM}
RW
mode or complementary PWM mode)
A/D trigger enable bit
This bit is disabled in PWM3 mode.
ADTRG _{(enabled in complementary PWM mode)}
RW
A/D trigger edge selection bit
This bit is disabled in PWM3 mode.
ADEG _{(enabled in complementary PWM mode)}
RW
External clock input selection bit
STCLK
Set this bit to 0 (external clock input
disabled) in PWM3 mode.
RW
PWM3 mode selection bit⁽²⁾
PWM3
Set this bit to 0 (PWM3 mode) in PWM3
mode.
RW
NOTES:
1. Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 (count stops).
2. When bits CMD1 to CMD0 are set to 00b (timer mode, PWM mode, or PWM3 mode), the setting of the PWM3 bit is
enabled.
Figure 14.100 Registers TRDMR and TRDFCR in PWM3 Mode
Rev.2.00 Aug 27, 2008 Page 240 of 458
REJ09B0250-0200