R8C20 Datasheet, PDF (196/501 Pages) Renesas Technology Corp – RENESAS MCU R8C FAMILY / R8C/2x SERIES

R8C/20 Group, R8C/21 Group
14. Timers
Timer RD Interrupt Enable Register i (i = 0 or 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
Address
After Reset
TRDIER0
TRDIER1
0144h
0154h
11100000b
11100000b
Bit Symbol
Bit Name
Function
RW
Input capture/compare match
0 : Disable an interrupt (IMIA) by the
interrupt enable bit A
IMIEA
IMFA bit
1 : Enable an interrupt (IMIA) by the
RW
IMFA bit
Input capture/compare match
0 : Disable an interrupt (IMIB) by the
interrupt enable bit B
IMIEB
IMFB bit
1 : Enable an interrupt (IMIB) by the
RW
IMFB bit
Input capture/compare match
0 : Disable an interrupt (IMIC) by the
interrupt enable bit C
IMIEC
IMFC bit
1 : Enable an interrupt (IMIC) by the
RW
IMFC bit
Input capture/compare match
0 : Disable an interrupt (IMID) by the
interrupt enable bit D
IMIED
IMFD bit
1 : Enable an interrupt (IMID) by the
RW
IMFD bit
Overflow /underflow interrupt
0 : Disable an interrupt (OVI) by the
enable bit
OVIE
OVF bit
1 : Enable an interrupt (OVI) by the
RW
OVF bit
—
Nothing is assigned. If necessary, set to 0.
(b7 - b5) When read, the content is 1.
—
Figure 14.42 Registers TRDIER0 to TRDIER1 in Input Capture Function
Timer RD Counter i (i = 0 or 1)⁽¹⁾
(b15)
(b8)
b7
b0 b7
b0
Symbol
Address
TRD0
TRD1
0147h-0146h
0157h-0156h
Function
Count a count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
NOTE:
1. Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
After Reset
0000h
0000h
Setting Range RW
0000h to FFFFh RW
Figure 14.43 Registers TRD0 to TRD1 in Input Capture Function
Rev.2.00 Aug 27, 2008 Page 180 of 458
REJ09B0250-0200