H83657 Datasheet, PDF (237/453 Pages) Renesas Technology Corp – single-chip microcomputers

Figure 9-36 shows an example of watchdog timer operations.
Example: ø = 4 MHz and the desired overflow period is 30 ms.
4 × 10⁶
8192
× 30 × 10^–3 = 14.6
The value set in TCW should therefore be 256 – 15 = 241 (H'F1).
H'FF
H'F1
TCW count
value
TCW overflow
H'00
Internal reset
signal
Start
H'F1 written
in TCW
H'F1 written in TCW
Reset
512 ø_OSC clock cycles
Figure 9-36 Typical Watchdog Timer Operations (Example)
9.6.4 Watchdog Timer Operation States
Table 9-21 summarizes the watchdog timer operation states.
Table 9-21 Watchdog Timer Operation States
Operation Mode
TCW
TCSRW
Reset
Reset
Reset
Active
Functions
Functions
Sleep
Functions
Functions
Watch
Halted
Retained
Sub-
active
Halted
Retained
Sub-
sleep
Standby
Halted Halted
Retained Retained
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