H83657 Datasheet, PDF (178/453 Pages) Renesas Technology Corp – single-chip microcomputers

9.4.2 Register Descriptions
1. Timer counter V (TCNTV)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TCNTV₇ TCNTV₆ TCNTV₅ TCNTV₄ TCNTV₃ TCNTV₂ TCNTV₁ TCNTV₀
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNTV is an 8-bit read/write up-counter which is incremented by internal or external clock input.
The clock source is selected by bits CKS2 to CKS0 in TCRV0. The TCNTV value can be read and
written by the CPU at any time. TCNTV can be cleared by an external reset signal, or by compare
match A or B. The clearing signal is selected by bits CCLR1 and CCLR0 in TCRV0.
When TCNTV overflows from H'FF to H'00, OVF is set to 1 in TCSRV.
TCNTV is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
2. Time constant registers A and B (TCORA, TCORB)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
TCORn₇ TCORn₆ TCORn₅ TCORn₄ TCORn₃ TCORn₂ TCORn₁ TCORn₀
1
1
1
1
1
1
1
1
R/W
R/W R/W
R/W R/W R/W
R/W R/W
n = A or B
TCORA and TCORB are 8-bit read/write registers.
TCORA and TCNTV are compared at all times, except during the T₃ state of a TCORA write cycle.
When the TCORA and TCNTV contents match, CMFA is set to 1 in TCSRV. If CMIEA is also set
to 1 in TCRV0, a CPU interrupt is requested.
Timer output from the TMOV pin can be controlled by a signal resulting from compare match,
according to the settings of bits OS3 to OS0 in TCSRV.
TCORA is initialized to H'FF upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
TCORB is similar to TCORA.
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