H83657 Datasheet, PDF (229/453 Pages) Renesas Technology Corp – single-chip microcomputers

3. Contention between OCR write and compare match
If a compare match is generated in the T₃ state of a write cycle to the lower byte of OCRA or
OCRB, the write to OCRA or OCRB takes precedence and the compare match signal is inhibited.
Figure 9-34 shows the timing.
OCR lower byte write cycle
T₁
T₂
T₃
ø
Address
Internal write
signal
FRC
OCR address
N
N+1
OCR
N
Internal compare
match signal
M
Write data
Inhibited
Figure 9-34 Contention between OCR Write and Compare Match
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