H83657 Datasheet, PDF (204/453 Pages) Renesas Technology Corp – single-chip microcomputers

IEOGA BUFEA IEDGC
FTIA
Edge detector
and internal
capture signal
generator
ICRC
ICRA
FRC
Figure 9-17 Buffer Operation (Example)
Table 9-16 Input Edge Selection during Buffer Operation
IEDGA
0
0
1
1
IEDGC
0
1
0
1
Input Edge Selection
Falling edge of input capture A input signal is captured (initial value)
Rising and falling edge of input capture A input signal are both captured
Rising edge of input capture A input signal is captured
ICRA to ICRD can be written and read by the CPU. Since they are 16-bit registers, data is
transferred from them to the CPU via a temporary register (TEMP). For details see 9.5.3, CPU
Interface.
To assure input capture, the pulse width of the input capture input signal must be at least 1.5 system
clocks (ø) when a single edge is selected, or at least 2.5 system clocks (ø) when both edges are
selected.
ICRA to ICRD are initialized to H'0000 upon reset and in standby mode, watch mode, subsleep
mode, and subactive mode.
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