M66592FP Datasheet, PDF (23/127 Pages) Renesas Technology Corp – ASSP (USB2.0 Peripheral Controller)

M66592FP/WG
The DMA0CFG register controls the input/output pins used for the DMA0 interface and the D0FIFO port, and the
DMA1CFG register controls the input/output pins used for the DMA1 interface and the D1FIFO port.
DMA0 pin configuration register [DMA0CFG]
<Address: 0CH>
DMA1 pin configuration register [DMA1CFG]
<Address: 0EH>
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DREQA BURST
DACKA
DFORM
DENDA PKTM DENDE
OBUS
?
0
0
?
?
0
0
0
0
0
0
0
?
0
?
?
?
-
-
?
?
-
-
-
-
-
-
-
?
-
?
?
?
-
-
?
?
-
-
-
-
-
-
-
?
-
?
?
?
-
0
?
?
0
0
0
0
0
0
0
?
0
?
?
Bit
Name
Function
S/W
15 Nothing is placed here. This should be fixed at “0”.
14 DREQA
DREQx_N signal polarity selection
13 BURST
Burst mode
This specifies the active state for the DREQx_N R/W
pin.
0: Low active
1: High active
0: Cycle steal transfer
R/W
1: Burst transfer
12-11 Nothing is placed here. These should be fixed at “0”.
10 DACKA
This specifies the active state for the DACKx_N R/W
DACKx_N signal polarity selection
pin.
0: Low active
1: High active
9-7 DFORM
DMA transfer signal selection
011: Only the DACKx_N signal is used (CPU R/W
bus).
000: The Address signal + the RD_N/WRx_
signals are used (CPU bus).
010: The DACKx_N + the RD_N/WRx_N
signals are used (CPU bus).
100: The DACKx_N signal is used (split bus).
110: The DACK0_N + the DSTB0_N signal are
used (split bus).
001, 101, 111: Reserved
6 DENDA
This specifies the active state of the DENDx_N R/W
DEND0_N signal polarity selection
pin.
0: Low active
1: High active
5 PKTM
0: The DENDx_N signal is asserted in transfer R/W
Packet mode
units.
1: The DENDx_N signal is asserted each time
an amount of data corresponding to the buffer
size is transferred.
4 DENDE
0: The DENDx_N signal is disabled (Hi-Z
R/W
DENDx_N signal enabled
output).
1: The DENDx_N signal is enabled.
3 Nothing is placed here. It should be fixed at “0”.
2 OBUS
0: The OBUS mode is enabled.
R/W
OBUS operation disabled
1: The OBUS mode is disabled.
1-0 Nothing is placed here. These should be fixed at "0”.
H/W Note
R
-
R 2.5.3
R
-
R 3.4.3.2
*3)
R
-
R 2.5.3
3.4.3.4
*2)
R 2.5.3
3.4.3.4
R
3.5
«Notes»
*2)
*3)
The PKTM bit is valid only when the data receiving direction (reading from the buffer memory) is set. If the
DxFIFO port is being used in the data writing direction, “PKTM=0” should be set.
The “DFORM=110” setting is valid only when the DMA channel 0 is set.
Also, the following should not be set: "DFORM=001”,"DFORM=101” and"DFORM=111”.
Rev1.00 2004.10.01 page 23 of 125