H8S-2172 Datasheet, PDF (226/570 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2100 Series

Bus release
DMA read DMA write Bus release
DMA read DMA write Bus release
φ
Address bus
Transfer source
Transfer
destination
Transfer source
Transfer
destination
DMA control Idle
Read Write
Idle
Read Write
Idle
Channel
Request
Request clearance period _Request
Request clearance period
Minimum 3 cycles
Minimum 3 cycles
[1]
[2] [3]
[4]
[5] [6]
[7]
Acceptance
resumed
Acceptance
resumed
[1] Acceptance after transfer enabling;
pin low level is sampled at rise of φ, and request is held.
[2], [5] Request is cleared at end of next bus cycle, and activation is started in DMAC.
[3], [6] DMA cycle is started.
[4], [7] Acceptance is resumed after completion of write cycle.
(As in [1],
pin low level is sampled at rise of φ, and request is held.)
Figure 7.22 Example of Normal Mode Transfer Activated by DREQ Pin Low Level
DREQ pin sampling is performed in each cycle starting at the next rise of φ after the end of the
DMMDR write cycle for setting the transfer-enabled state.
When a low level is sampled at the DREQ pin while acceptance via the DREQ pin is possible, the
request is held within the DMAC. Then when activation is initiated within the DMAC, the request
is cleared. At the end of the write cycle, acceptance resumes and DREQ pin low level sampling is
performed again; this sequence of operations is repeated until the end of the transfer.
Figure 7.23 shows an example of block transfer mode transfer activated by the DREQ pin low
level.
Rev. 2.00, 03/04, page 194 of 534