H8S-2172 Datasheet, PDF (187/570 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer H8S Family H8S-2100 Series

Figure 7.1 shows a block diagram of the DMAC.
Bus controller
External pins
On-chip USB module
Internal signals with
on-chip USB module
Interrupt request
signals to CPU
for individual channels
Data buffer
Control logic
DMMDR_n
DMACR_n
Address buffer
Processor
DMSAR_n
DMDAR_n
DMTCR_n
Internal data bus
Legend
DMSAR_n: DMA source address register
DMDAR_n: DMA destination address register
DMTCR_n: DMA transfer count register
DMMDR_n: DMA mode control register
DMACR_n: DMA address control register
: DMA transfer request
:
acceptance acknowledge
: DMA transfer end
: DMA transfer acknowledge
n = 0 to 3
Figure 7.1 Block Diagram of DMAC
7.2 Input/Output Pins
Table 7.1 shows the pin configuration of the DMAC.
The corresponding port to the DACK pin automatically enters the output state by the setting of the
single address transfer mode. When the DREQ pin is used, the corresponding port must not enter
the output state. Whether the corresponding port to the TEND/DRAK pin is used as TEND/DRAK
pin can be set by the register.
Rev. 2.00, 03/04, page 155 of 534