H8SX1520R Datasheet, PDF (221/826 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

Section 7 DMA Controller (DMAC)
7.4.10 Bus Cycles in Dual Address Mode
(1) Normal Transfer Mode (Cycle Stealing Mode)
In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one
word, or one longword) is completed. One bus cycle or more by the CPU are executed in the bus
released cycles.
In figure 7.24, the TEND signal output is enabled and data is transferred in words from the
external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer
mode by cycle stealing.
Bφ
Address
bus
DMA read DMA write
cycle
cycle
DMA read DMA write
cycle
cycle
DMA read DMA write
cycle
cycle
RD
LHWR,
LLWR
TEND
Bus
released
Bus
released
Bus
released
Last transfer cycle Bus
released
Figure 7.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing
In figures 7.25 and 7.26, the TEND signal output is enabled and data is transferred in longwords
from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal
transfer mode by cycle stealing.
In figure 7.25, the transfer source (DSAR) is not aligned with a longword boundary and the
transfer destination (DDAR) is aligned with a longword boundary.
In figure 7.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer
destination (DDAR) is not aligned with a longword boundary.
Rev. 1.00 Mar. 06, 2006 Page 183 of 784
REJ09B0282-0100