H8SX1520R Datasheet, PDF (152/826 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

Section 5 Interrupt Controller
5.6.3 Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example is for the case where
interrupt control mode 0 is set in maximum mode, and the program area and stack area are in on-
chip memory.
Figure 5.5 Interrupt Exception Handling
Rev. 1.00 Mar. 06, 2006 Page 114 of 784
REJ09B0282-0100