H8SX1520R Datasheet, PDF (140/826 Pages) Renesas Technology Corp – 32-Bit CISC Microcomputer H8SX Family H8SX/1500 Series

Section 5 Interrupt Controller
Corresponding bit
in ICR
Input buffer
IRQn input
IRQnSF, IRQnSR
Edge/level
detection circuit
IRQnE
IRQnF
S
Q
R
IRQn interrupt request
[Legend]
n = 14 to 0
Clear signal
Figure 5.2 Block Diagram of Interrupts IRQn
When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn
should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn
to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed
when the corresponding input signal IRQn is set to high before the interrupt handling begins.
5.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that enable or disable these interrupts. They can be controlled independently.
When the enable bit is set to 1, an interrupt request is issued to the interrupt controller.
• The interrupt priority can be set by means of IPR.
• The DMAC can be activated by a TPU, SCI, RCAN-ET, SSU, or other interrupt request.
• DMAC activation can be controlled by the CPU priority control function over the DMAC.
Rev. 1.00 Mar. 06, 2006 Page 102 of 784
REJ09B0282-0100