3825_03 Datasheet, PDF (197/339 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

APPLICATION
2.5 Serial I/O
sReceive enable bit (bit 5)
This bit controls receive operation. This bit controls as shown in Table 2.5.4 only when the serial
I/O enable bit (bit 7) is “1” (serial I/O enabled). When the serial I/O enable bit is “0” (serial I/O
disabled), this bit is invalid.
Table 2.5.4 Control contents of receive enable bit
Receive enable bit
P44/RXD pin function
Receive buffer full flag ^V1
0
Port P44
Set to “0”
1
Data receive pin RXD Flag function is valid
V1: Bit 1 of serial I/O status register
V2: Bits 3, 4, 5, and 6 of serial I/O status register
Each error flag^V2
sSerial I/O mode selection bit (bit 6)
This bit selects a transmit/receive mode of the serial I/O. In the UART mode, set this bit to “0.” In the
clock synchronous mode, set it to “1.”
sSerial I/O enable bit (bit 7)
When the serial I/O function is used, set this bit to “1.”
When the bit is set to “1,” the pins P44/RxD, P45/TxD, and P46/SCLK function as RxD, TxD, and SCLK
respectively (Furthermore, when the SRDY output enable bit is set to “1,” the P47/SRDY pin functions
as an SRDY pin).
In the “0” state, they function as ports P44–P47 respectively.
3825 GROUP USER’S MANUAL
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