3825_03 Datasheet, PDF (10/339 Pages) Renesas Technology Corp – 8-BIT SINGLE-CHIP MICROCOMPUTER

List of figures
List of figures
CHAPTER 1. HARDWARE
Fig. 1 Pin configuration of M38254M6-XXXFP .................................................................................. 1-2
Fig. 2 Pin configuration of M38254M6-XXXGP ................................................................................. 1-3
Fig. 3 Function block diagram ........................................................................................................... 1-4
Fig. 4 Part numbering ........................................................................................................................ 1-7
Fig. 5 Memory expansion plan (1) ..................................................................................................... 1-8
Fig. 6 Memory expansion plan (2) ..................................................................................................... 1-9
Fig. 7 Structure of CPU mode register ............................................................................................ 1-10
Fig. 8 Memory map diagram ............................................................................................................1-11
Fig. 9 Memory map of special function register (SFR) .................................................................... 1-12
Fig. 10 Structure of PULL register A and PULL register B .............................................................. 1-13
Fig. 11 Port block diagram (1) ......................................................................................................... 1-15
Fig. 12 Port block diagram (2) ......................................................................................................... 1-16
Fig. 13 Interrupt control ...................................................................................................................1-18
Fig. 14 Structure of interrupt-related registers ................................................................................. 1-18
Fig. 15 Connection example when using key input interrupt and port P2 block diagram ................ 1-19
Fig. 16 Timer block diagram ............................................................................................................1-20
Fig. 17 Structure of timer X mode register ....................................................................................... 1-21
Fig. 18 Structure of timer Y mode register ....................................................................................... 1-22
Fig. 19 Structure of timer 123 mode register ................................................................................... 1-23
Fig. 20 Block diagram of clock synchronous serial I/O .................................................................... 1-24
Fig. 21 Operation of clock synchronous serial I/O function ............................................................. 1-24
Fig. 22 Block diagram of UART serial I/O ........................................................................................1-25
Fig. 23 Operation of UART serial I/O function ................................................................................. 1-25
Fig. 24 Structure of serial I/O control registers ................................................................................ 1-27
Fig. 25 Structure of A-D control register .......................................................................................... 1-28
Fig. 26 A-D converter block diagram ...............................................................................................1-28
Fig. 27 Structure of segment output enable register and LCD mode register ................................. 1-29
Fig. 28 Block diagram of LCD controller/driver ................................................................................ 1-30
Fig. 29 Example of circuit at each bias ............................................................................................ 1-31
Fig. 30 LCD display RAM map ........................................................................................................ 1-32
Fig. 31 LCD drive waveform (1/2 bias) ............................................................................................ 1-33
Fig. 32 LCD drive waveform (1/3 bias) ............................................................................................ 1-34
Fig. 33 Structure of clock output control register ............................................................................. 1-35
Fig. 34 Clock output function block diagram .................................................................................... 1-35
Fig. 35 Example of reset circuit ....................................................................................................... 1-36
Fig. 36 Internal state of microcomputer immediately after reset ...................................................... 1-36
Fig. 37 Reset sequence ...................................................................................................................1-37
Fig. 38 Ceramic resonator circuit ..................................................................................................... 1-38
Fig. 39 External clock input circuit ................................................................................................... 1-38
Fig. 40 Clock generating circuit block diagram ................................................................................ 1-39
Fig. 41 State transitions of internal clock φ ............................................................................................... 1-40
Fig. 42 Programming and testing of One Time PROM version ....................................................... 1-42
Fig. 43 Circuit for measuring output switching characteristics ........................................................ 1-54
Fig. 44 Timing diagram .................................................................................................................... 1-55
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3825 GROUP USER’S MANUAL