HN58X2508I Datasheet, PDF (19/29 Pages) Renesas Technology Corp – Electrically Erasable and Programmable Read Only Memory

HN58X2508I/HN58X2516I
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low.
The bits of the instruction byte and the address bytes are then shifted in, on serial data input (D). The
addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on
serial data output (Q).
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and
the byte of data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be
continued indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can
occur at any time during the cycle. The addressed first byte can be any byte within any page. The instruction
is not accepted, and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
Q
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
A15 A14 A13 A3 A2 A1 A0
High-Z
Data Out 1
Data Out 2
7 6 5 4 3 21 07
Note: 1. Depending on the memory size, as shown in the following table, the most significant address bits
are don’t care.
Address Range Bits
Device
HN58X2516I
Address bits
A10 to A0
Notes: 1. b15-b11 are don’t care on the HN58X2516
2. b15-b10 are don’t care on the HN58X2508
HN58X2508I
A9 to A0
Rev.2.00, Aug.19.2004, page 19 of 27