HN58X2508I Datasheet, PDF (16/29 Pages) Renesas Technology Corp – Electrically Erasable and Programmable Read Only Memory

HN58X2508I/HN58X2516I
Read Status Register(RDSR):
The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may
be read at any time, even while a Write or Write Status Register cycle is in progress. When one of these
cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new
instruction to the device. It is also possible to read the Status Register continuously, as shown in the
following figure.
Read Status Register (RDSR) Sequence
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
Q
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
High-Z
Status Register Out
7 6 5 4 32 1 07
The status and control bits of the Status Register are as follows:
WIP bit: The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write Status
Register cycle. When set to 1, such a cycle is in progress. When reset to 0, no such cycles are in progress.
WEL bit: The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When
set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write Enable Latch is reset and no
Write or Write Status Register instructions are accepted.
BP1, BP0 bits: The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status Register (WRSR)
instruction. When one or both of the Block Protect (BP1, BP0) bits are set to 1, the relevant memory area (as
defined in the Status Register Format table) becomes protected against Write (WRITE) instructions. The
Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set.
Rev.2.00, Aug.19.2004, page 16 of 27