M16C_11 Datasheet, PDF (18/112 Pages) Renesas Technology Corp – televisions, household appliances, office equipment, communication devices

M16C/65C Group
1. Overview
1.6 Pin Functions
Table 1.12 Pin Functions for the 128-Pin Package (1/3)
Signal Name Pin Name I/O Power Supply
Description
Power supply
input
VCC1,
VCC2,
I
VSS
-
Apply 2.7 to 5.5 V to pins VCC1 and VCC2 (VCC1 ≥ VCC2),
and 0 V to the VSS pin.
Analog power
supply input
Reset input
AVCC,
AVSS
I
RESET
I
VCC1
VCC1
This is the power supply for the A/D and D/A converters.
Connect the AVCC pin to VCC1, and connect the AVSS pin
to VSS.
Driving this pin low resets the MCU.
CNVSS
CNVSS
I
VCC1
Input pin to switch processor modes. After a reset, to start
operating in single-chip mode, connect the CNVSS pin to
VSS via a resistor. To start operating in microprocessor
mode, connect the pin to VCC1.
Input pin to select the data bus of the external area. The data
External data bus
width select input
BYTE
I
VCC1
bus is 16 bits when it is low and 8 bits when it is high. This
pin must be fixed either high or low. Connect the BYTE pin to
VSS in single-chip mode.
D0 to D7 I/O
VCC2
Inputs or outputs data (D0 to D7) while accessing an
external area with a separate bus.
D8 to D15 I/O
VCC2
Inputs or outputs data (D8 to D15) while accessing an
external area with a 16-bit separate bus.
A0 to A19
O
VCC2 Outputs address bits A0 to A19.
A0/D0 to
A7/D7
I/O
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A0 to A7) by timesharing, while accessing an external area
with an 8-bit multiplexed bus.
Bus control
pins
A1/D0 to
A8/D7
I/O
CS0 to CS3 O
WRL/WR
WRH/BHE O
RD
VCC2
VCC2
VCC2
Inputs or outputs data (D0 to D7) and outputs address bits
(A1 to A8) by timesharing, while accessing an external area
with a 16-bit multiplexed bus.
Outputs chip-select signals CS0 to CS3 to specify an
external area.
Outputs WRL, WRH, (WR, BHE), and RD signals. WRL and
WRH can be switched with BHE and WR.
• WRL, WRH, and RD selected
If the external data bus is 16 bits, data is written to an even
address in an external area when WRL is driven low. Data
is written to an odd address when WRH is driven low. Data
is read when RD is driven low.
• WR, BHE, and RD selected
Data is written to an external area when WR is driven low.
Data in an external area is read when RD is driven low. An
odd address is accessed when BHE is driven low. Select
WR, BHE, and RD when using an 8-bit external data bus.
ALE
O
VCC2 Outputs an ALE signal to latch the address.
HOLD
I
VCC2
HOLD input is unavailable. Connect the HOLD pin to VCC2
via a resistor (pull-up).
HLDA
O
VCC2 In a hold state, HLDA outputs a low-level signal.
RDY
I
VCC2
The MCU bus is placed in wait state while the RDY pin is
driven low.
Power supply: VCC2 is used to supply power to the external bus associated pins. The dual power supply configuration
allows VCC2 to interface at a different voltage than VCC1.
R01DS0015EJ0100 Rev.1.00
Feb 07, 2011
Page 18 of 109