R1EX25512ASA00I_15 Datasheet, PDF (15/22 Pages) Renesas Technology Corp – Serial Peripheral Interface 512K EEPROM (64-Kword × 8-bit)

R1EX25512ASA00I/R1EX25512ATA00I
Write to Memory Array (WRITE):
As shown in the following figures, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (D).
The instruction is terminated by driving chip select (S) high at a byte boundary of the input data. In the case of the first
figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to
write a single byte. The self-timed Write cycle starts, and continues for a period t_W (as specified in AC Characteristics).
At the end of the cycle, the Write In Progress (WIP) bit is reset to 0.
If, though, chip select (S) continues to be driven low, as shown in the second figure, the next byte of the input data is
shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be
written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address counter are incremented. If the
number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the
beginning of the page, and the previous data there are overwritten with the incoming data. (The page size of these
device is 128 bytes).
The instruction is not accepted, and is not executed, under the following conditions:
 If the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable instruction just before)
 If a Write cycle is already in progress
 If the device is deselected
 If the addressed page is in the region protected by the Block Protect (BP1 and BP0) bits.
Byte Write (WRITE) Sequence (1 Byte)
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
Data Byte 1
15 14 13 3 2 1 0 7 6 5 4 3 2 1 0
Q
High-Z
Note: 1. The memory size is shown in the Address Range Bits table.
R10DS0044EJ0100 Rev.1.00
Oct.04, 2010
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