R1EX25512ASA00I_15 Datasheet, PDF (14/22 Pages) Renesas Technology Corp – Serial Peripheral Interface 512K EEPROM (64-Kword × 8-bit)

R1EX25512ASA00I/R1EX25512ATA00I
Read from Memory Array (READ):
As shown in the following figure, to send this instruction to the device, chip select (S) is first driven low. The bits of
the instruction byte and the address bytes are then shifted in, on serial data input (D). The addresses are loaded into an
internal address register, and the byte of data at that address is shifted out, on serial data output (Q).
If chip select (S) continues to be driven low, the internal address register is automatically incremented, and the byte of
data at the new address is shifted out.
When the highest address is reached, the address counter rolls over to zero, allowing the Read cycle to be continued
indefinitely. The whole memory can, therefore, be read with a single READ instruction.
The Read cycle is terminated by driving chip select (S) high. The rising edge of the chip select (S) signal can occur at
any time during the cycle. The addressed first byte can be any byte within any page. The instruction is not accepted,
and is not executed, if a Write cycle is currently in progress.
Read from Memory Array (READ) Sequence
V_IH
S
V_IL
V_IH
W
V_IL
V_IH
C
V_IL
V_IH
D
V_IL
Q
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16-Bit Address
15 14 13 3 2 1 0
High-Z
Data Out 1
Data Out 2
7 6 5 4 3 21 07
Note: 1. The memory size is shown in the following table.
Address Range Bits
Address bits
Device
A15 to A0
R1EX25512A
R10DS0044EJ0100 Rev.1.00
Oct.04, 2010
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