H8S33 Datasheet, PDF (1046/1489 Pages) Renesas Technology Corp – Renesas 16-Bit Single-Chip Microcomputer

Section 23A Clock Pulse Generator (H8S/2633, H8S/2632, H8S/2631, H8S/2633F)
23A.1.2 Register Configuration
The clock pulse generator is controlled by SCKCR and LPWRCR. Table 23A.1 shows the register
configuration.
Table 23A.1 Clock Pulse Generator Register
Name
Abbreviation R/W
System clock control register
SCKCR
R/W
Low-power control register
LPWRCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'00
H'00
Address^*
H'FDE6
H'FDEC
23A.2 Register Descriptions
23A.2.1 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
3
2
1
0
PSTOP —
—
—
STCS SCK2 SCK1 SCK0
Initial value:
0
0
0
0
0
0
0
0
R/W
: R/W
—
—
—
R/W
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that performs φ clock output control, selection of
operation when the PLL circuit frequency multiplication factor is changed, and medium-speed
mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—φ Clock Output Disable (PSTOP): Controls φ output.
Bit 7
PSTOP
0
1
Description
High-Speed Mode,
Medium-Speed Mode, Sleep Mode
Subactive Mode
Subsleep Mode
Software
Standby Mode,
Watch Mode,
Hardware
Direct Transitions Standby Mode
φ output (initial value) φ output
Fixed high
High impedance
Fixed high
Fixed high
Fixed high
High impedance
Rev. 5.00 Mar 28, 2005 page 982 of 1422
REJ09B0234-0500