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HYB18TC1G800BF_07 Datasheet, PDF (9/65 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM | |||
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Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
Ball#
Name
Ball
Type
J2
VREF
Al
J1
VDDL
PWR
J7
VSSDL
PWR
Not Connected Ã8 Organization
A1, A2, A8, A9, NC
NC
R7, W1, W2,
W8, W9, R3
Other Balls Ã8 Organizations
K9
ODT
I
Buffer
Type
â
â
â
â
SSTL
Function
I/O Reference Voltage
Power Supply
Power Supply
Not Connected
On-Die Termination Control
Abbreviation
I
O
I/O
AI
PWR
GND
NC
Description
Standard input-only ball. Digital levels.
Output. Digital levels.
I/O is a bidirectional input/output signal.
Input. Analog levels.
Power
Ground
Not Connected
TABLE 7
Abbreviations for Ball Type
Abbreviation
SSTL
LV-CMOS
CMOS
OD
TABLE 8
Abbreviations for Buffer Type
Description
Serial Stub Terminated Logic (SSTL_18)
Low Voltage CMOS
CMOS Levels
Open Drain. The corresponding ball has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR.
Rev. 1.21, 2007-07
9
02282007-F8UP-4HSU
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