HYB18TC1G800BF_07 Datasheet, PDF (47/65 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
FIGURE 9
Differential input waveform timing - t_lS and t_lH
&.
&.
W,6  W,+ 
W,6 W,+ 
9_' _{'4 }
9_,_{+DF }PLQ
9_,_{+GF }PLQ
9₅ _()GF
9_,_{/GF }PD[ 
9_,_{/DF }PD[ 
9₆ _6
Parameter
TABLE 50
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Symbol
DDR2–533
Min.
Max.
Unit
Note^1)2)3)4)5)
6)
DQ output access time from CK / CK
t_AC
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width
t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery + precharge t_DAL
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_DELAY
DQ and DM input hold time (differential data t_DH(base)
strobe)
DQ and DM input hold time (single ended data t_DH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
t_DIPW
t_DQSCK
t_DQSL,H
t_DQSQ
Write command to 1st DQS latching transition t_DQSS
DQ and DM input setup time (differential data t_DS(base)
strobe)
DQ and DM input setup time (single ended data t_DS1(base)
strobe)
–500
2
0.45
3
0.45
WR + t_RP
t_IS + t_CK + t_IH
225
–25
0.35
–450
0.35
—
– 0.25
100
–25
+500
—
0.55
—
0.55
—
––
––
—
—
+450
—
300
+ 0.25
—
—
ps
t_CK
t_CK
t_CK
t_CK
t_CK
7)17)
ns
8)
ps
9)
ps
10)
t_CK
ps
t_CK
ps
10)
t_CK
ps
10)
ps
10)
Rev. 1.21, 2007-07
47
02282007-F8UP-4HSU