HYB18TC1G800BF_07 Datasheet, PDF (43/65 Pages) Qimonda AG – 1-Gbit Double-Data-Rate-Two SDRAM

Internet Data Sheet
HYB18TC1G[80/16]0BF
1-Gbit Double-Data-Rate-Two SDRAM
30) For these parameters, the DDR2 SDRAM device is characterized and verified to support t_nPARAM = RU{t_PARAM / t_CK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support t_nRP = RU{t_RP / t_CK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which t_RP = 15 ns, the device will support
t_nRP = RU{t_RP / t_CK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
31) t_WTR is at lease two clocks (2 x t_CK) independent of operation frequency.
Parameter
TABLE 49
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Symbol
DDR2–667
Unit
Note^{1)2)3)4)5)6)7)}
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
t_AC
t_CCD
t_CH.AVG
t_CK.AVG
t_CKE
Average clock low pulse width
Auto-Precharge write recovery + precharge time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
t_CL.AVG
t_DAL
t_DELAY
DQ and DM input hold time
t_DH.BASE
DQ and DM input pulse width for each input
t_DIPW
DQS output access time from CK / CK
t_DQSCK
DQS input high pulse width
t_DQSH
DQS input low pulse width
t_DQSL
DQS-DQ skew for DQS & associated DQ signals t_DQSQ
DQS latching rising transition to associated clock t_DQSS
edges
DQ and DM input setup time
t_DS.BASE
DQS falling edge hold time from CK
t_DSH
DQS falling edge to CK setup time
t_DSS
Four Activate Window for 1KB page size products t_FAW
Four Activate Window for 2KB page size products t_FAW
CK half pulse width
t_HP
Data-out high-impedance time from CK / CK
t_HZ
Address and control input hold time
t_IH.BASE
Control & address input pulse width for each input t_IPW
Address and control input setup time
t_IS.BASE
DQ low impedance time from CK/CK
t_LZ.DQ
DQS/DQS low-impedance time from CK / CK
t_LZ.DQS
MRS command to ODT update delay
t_MOD
Mode register set command cycle time
t_MRD
Min.
–450
2
0.48
3000
3
Max.
+450
—
0.52
8000
—
0.48
WR + t_nRP
t_IS + t_{CK .AVG} +
t_IH
175
0.35
–400
0.35
0.35
—
– 0.25
0.52
—
—
––
—
+400
—
—
240
+ 0.25
100
0.2
0.2
37.5
50
Min(t_CH.ABS,
t_CL.ABS)
—
275
0.6
200
2 x t_AC.MIN
t_AC.MIN
0
2
––
—
—
—
—
__
t_AC.MAX
—
—
—
t_AC.MAX
t_AC.MAX
12
—
ps
8)
nCK
t_CK.AVG
ps
nCK
9)10)
11)
t_CK.AVG
nCK
ns
9)10)
12)13)
ps
t_CK.AVG
ps
t_CK.AVG
t_CK.AVG
ps
t_CK.AVG
18)19)14)
8)
15)
16)
ps
t_CK.AVG
t_CK.AVG
ns
ns
ps
17)18)19)
16)
16)
30)
30)
20)
ps
ps
t_CK.AVG
ps
ps
ps
ns
nCK
8)21)
24)22)
23)24)
8)21)
8)21)
30)
Rev. 1.21, 2007-07
43
02282007-F8UP-4HSU